

#ifndef _FH_MSHC_LITE_H_
#define _FH_MSHC_LITE_H_


#include <common.h>
#include <clk.h>
#include <dm.h>
#include <malloc.h>
#include <sdhci.h>

#include <asm/arch/hardware.h>
#include <mmc.h> 

struct fh_mshc_lite{
	void *ctrl_regs;
	void *phy_regs;
	struct mshc_lite_plat_info *plat;
	struct sdhci_host *bind_host;
	struct mshc_lite_emmc_card_info *bind_active_tuning_emmc;
	//here will check if board has tuning already
	//char bind_emmc_name[4];
};

struct fh_mshc_phy_dll{
	u32 tx_dly;
	u32 rxdata_dly;
	u32 rxcmd_dly;
};

//xfer_area;
enum {
	USER_AREA_ACCESS = 0,
	BOOT_1_ACCESS = 1,
	BOOT_2_ACCESS = 2,
//RPMB_ACCESS = 3,
};


#ifndef CONFIG_AUTO_TUNING_EMMC_AREA
#define CONFIG_AUTO_TUNING_EMMC_AREA BOOT_2_ACCESS
#endif

#define	MAX_TX_DELAY_LINE_SIZE	0x100
#define	MAX_RX_DELAY_LINE_SIZE	0x100
#ifndef CONFIG_AUTO_TUNING_EMMC_ADDR
#define CONFIG_AUTO_TUNING_EMMC_ADDR 0x0
#endif




#define AUTO_FIX_TEST_PASS_TIME	3

#define PHY_MAX_BIT_WIDTH_1		0
#define PHY_MAX_BIT_WIDTH_4		1
#define PHY_MAX_BIT_WIDTH_8		3

#define PHY_TX_DRI_SEL_CLK_EMMC		0
#define PHY_TX_DRI_SEL_CLK_EMMC_2X	1

#define PHY_RX_DATA_SEL_CLK_EMMC	0
#define PHY_RX_DATA_SEL_CLK_DS		1

#define PHY_RX_CMD_SEL_CLK_EMMC		0
#define PHY_RX_CMD_SEL_CLK_DS		1

#define PHY_TX_DRI_INV_ENABLE	1
#define PHY_TX_DRI_INV_DISABLE	0

#define PHY_RX_DATA_SAMPLE_INV_ENABLE	1
#define PHY_RX_DATA_SAMPLE_INV_DISABLE	0

#define PHY_RX_CMD_SAMPLE_INV_ENABLE	1
#define PHY_RX_CMD_SAMPLE_INV_DISABLE	0

#define PHY_BY_PASS_DELAY_FUNC	0xdeadbeef

#define INIT_INV_ENABLE			1
#define INIT_INV_DISABLE		0

#define FH_SDHC_MIN_FREQ	400000
#define FH_SDHCI_MAX_FREQ  200000000

//if emmc es mode enable, set cmd clk from emmc ds
#define EMMC_ES_MODE_ENABLE		1
#define EMMC_ES_MODE_DISABLE	0


void phy_dly_setting(struct fh_mshc_lite *p_mshc, u32 tx_dly, u32 rxdata_dly, u32 rxcmd_dly);
void mshc_phy_init(struct fh_mshc_lite *p_mshc, int inv_en);
void fh_mshc_tuning_set_clock(struct sdhci_host *host, u32 clock, u32 timing, u32 width, u32 es_mode);
void fh_mshc_tuning_ctrl_init(struct sdhci_host *host);
void dump_est_csd_reg(u8 *p_u8);
void fh_mshc_hs_setting(struct sdhci_host *host, u32 clock, u32 width, u32 es_mode, u32 timing, struct fh_mshc_phy_dll *p_dll);
void fh_mshc_hs200_setting(struct sdhci_host *host, u32 clock, u32 width, u32 es_mode, u32 timing, struct fh_mshc_phy_dll *p_dll);
void fh_mshc_hs400_setting(struct sdhci_host *host, u32 clock, u32 width, u32 es_mode, u32 timing, struct fh_mshc_phy_dll *p_dll);
#endif
